1. Field of the Invention
The present disclosure generally relates to the formation of integrated circuits, and, more particularly, to a back end of line processing for providing a bump structure arranged for direct solder bump connection in a die area while enabling wire bonding of bond pads located outside the die area, such as the frame region of semiconductor devices.
2. Description of the Related Art
In manufacturing integrated circuits, it is usually necessary to package a chip and provide leads and terminals for connecting the chip circuitry with the periphery. In some packaging techniques, chips, chip packages or other appropriate units may be connected by means of solder balls, formed from so-called solder bumps, that are formed on a corresponding layer of at least one of the units, for instance, on a dielectric passivation layer of the microelectronic chip. In order to connect the microelectronic chip with the corresponding carrier, the surfaces of two respective units to be connected, i.e., the microelectronic chip comprising, for instance, a plurality of integrated circuits, and a corresponding package, have formed thereon adequate pad arrangements to electrically connect the two units after reflowing the solder bumps provided at least on one of the units, for instance, on the microelectronic chip. In other techniques, solder bumps may have to be formed that are to be connected to corresponding wires, or the solder bumps may be brought into contact with corresponding pad areas of another substrate acting as a heat sink. Consequently, it may be necessary to form a large number of solder bumps that may be distributed over the entire chip area, thereby providing, for example, the I/O (input/output) capability as well as the desired low-capacitance arrangement required for high frequency applications of modern microelectronic chips that usually include complex circuitry, such as microprocessors, storage circuits and the like, and/or include a plurality of integrated circuits forming a complete complex circuit system.
In modern integrated circuits, highly conductive metals, such as copper and alloys thereof, are used to accommodate the high current densities encountered during the operation of the devices. Consequently, the metallization layers may comprise metal lines and vias formed from copper or copper alloys, wherein the last metallization layer may provide contact areas for connecting to the solder bumps to be formed above the copper-based contact areas. The processing of copper in the subsequent process flow for forming the solder bumps, which is itself a highly complex manufacturing phase, may be performed on the basis of the well-established metal aluminum that has effectively been used for forming solder bump structures in complex aluminum-based microprocessors. For this purpose, an appropriate barrier and adhesion layer is formed on the copper-based contact area, followed by an aluminum layer. Subsequently, the contact layer including the solder bumps is formed on the basis of the aluminum-covered contact area.
In order to provide hundreds or thousands of mechanically well-fastened solder bumps on corresponding pads, the attachment procedure of the solder bumps requires a careful design since the entire device may be rendered useless upon failure of only one of the solder bumps. For this reason, one or more carefully chosen layers are generally placed between the solder bumps and the underlying substrate or wafer including the aluminum-covered contact areas. In addition to the important role these interfacial layers, herein also referred to as underbump metallization layers, may play in endowing a sufficient mechanical adhesion of the solder bump to the underlying contact area and the surrounding passivation material, the underbump metallization has to meet further requirements with respect to diffusion characteristics and current conductivity. Regarding the former issue, the underbump metallization layer has to provide an adequate diffusion barrier to prevent the solder material, frequently a mixture of lead (Pb) and tin (Sn), from attacking the chip's underlying metallization layers and thereby destroying or negatively affecting their functionality. Moreover, migration of solder material, such as lead, to other sensitive device areas, for instance into the dielectric, where a radioactive decay in lead may also significantly affect the device performance, has to be effectively suppressed by the underbump metallization. Regarding current conductivity, the underbump metallization, which serves as an interconnect between the solder bump and the underlying metallization layer of the chip, has to exhibit a thickness and a specific resistance that does not inappropriately increase the overall resistance of the metallization pad/solder bump system. In addition, the underbump metallization will serve as a current distribution layer during electroplating of the solder bump material. Electroplating is presently the preferred deposition technique, since physical vapor deposition of solder bump material, which is also used in the art, requires a complex mask technology in order to avoid any misalignments due to thermal expansion of the mask while it is contacted by the hot metal vapors. Moreover, it is extremely difficult to remove the metal mask after completion of the deposition process without damaging the solder pads, particularly when large wafers are processed or the pitch between adjacent solder pads decreases.
The complexity of advanced semiconductor devices, such as CPUs and the like, typically requires the provision of specifically designed test structures for estimating the quality and thus reliability of the manufacturing flow and the materials used. As one important example for a front end of line process, the gate dielectrics of field effect transistors may be mentioned, the quality of which has to be monitored in order to enable an assessment of the operational behavior of the transistor devices. Similarly, many back end of line processes may require a thorough monitoring, such as the electromigration behavior, or generally stress-induced degradation of sophisticated wiring structures, in particular, as typically increasingly low-k dielectric materials are used in the wiring level in combination with highly conductive metals, such as copper and the like. The specifically designed test structures are typically not provided within the actual die region to avoid consumption of precious chip area, but are positioned in the periphery, such as the scribe lane for dicing the substrate prior to packaging. Although the direct connection of the die area with an appropriate carrier substrate via the bump structure is a preferred technique for complex circuits, the assembly of the test structure may typically be accomplished on the basis of well-approved wire bond techniques, since wire bonding of the test structures to respective packages may be cheaper and faster compared to a direct solder bump connection. Moreover, generally the pitch between bond pads may be selected less compared to an arrangement of solder bumps in the test structure.
Wire bonding techniques are well established for aluminum-based bond pads, while also well-established techniques are available for forming solder bump structures on the basis of aluminum. On the other hand, since the formation of aluminum-based solder bump structures may result in a more complex process flow compared to approaches for directly forming bump structures on the basis of copper-based contact areas in sophisticated metallization systems provided on the basis of copper, possibly in combination with low-k dielectric materials, great efforts are being made in establishing process techniques for avoiding the usage of aluminum in the back end of line (BEOL) process. However, a bonding on copper bond pads is very difficult to achieve due to an inhomogeneous self-oxidization of the copper surface in combination with extensive corrosion, which may result in highly non-reliable bond connections. For this reason, metallization systems including actual die regions and respective test structures may nevertheless be manufactured on the basis of aluminum in an attempt to utilize well-established infrastructure of aluminum-based bump structure techniques in combination with well-approved wire bond processes, thereby however contributing to enhanced process complexity for copper-based metallization systems, as will be described in more detail with reference to FIGS. 1a-1d. 
FIG. 1a schematically illustrates a cross-sectional view of a conventional semiconductor device 100 in an advanced manufacturing stage. The semiconductor device 100 comprises a substrate 101, which may have formed therein circuit elements and other microstructural features that are, for convenience, not shown in FIG. 1a. Moreover, the device 100 comprises one or more metallization layers including copper-based metal lines and vias wherein, for convenience, the very last metallization layer 107 is shown, which may comprise a dielectric material 107A having formed therein a first copper-based metal region 107D and a second copper-based metal region 107T. That is, the metal regions 107D and 107T may be formed of copper or a copper alloy, possibly in combination with respective barrier materials (not shown), so as to suppress any interaction between the dielectric material 107A and the copper material. The metal region 107D may be electrically connected to any circuit elements representing an integrated circuit in accordance with a specific circuit arrangement, while the metal region 107T may represent a contact area connected to respective device features representing a test structure to characterize specific device properties, such as electromigration performance, reliability of gate dielectrics and the like. Thus, the portion of the metallization layer 107 including the contact area 107D may correspond to a die or device region 150D, while the portion of the metallization layer 107 comprising the contact area 107T may correspond to a test region 150T of the device 100. For example, the device region 150D may represent a die region, which may, after dicing the device 100 into separate entities, represent a single functional unit, while the test region 150T, which may not be operationally connected to the device region 150D, may represent a respective area in the device 100 that may not be utilized when operating a respective circuit in the device region 150D. For instance, the device region 150D may represent a die area which is separated from the test region 150T by a die seal (not shown) which is typically used for protecting an actual die area from being damaged during dicing the substrate.
The semiconductor device 100 further comprises a cap layer 106 that is formed of an appropriate material, such as silicon nitride, silicon carbide, nitrogen-containing silicon carbide and the like, so as to confine the copper material of the non-exposed portions of the contact areas 107D, 107T. Moreover, a first passivation layer 103A is provided, for instance, comprised of silicon dioxide, silicon oxynitride and the like. Furthermore, a second passivation layer 103B may be provided, for instance in the form of silicon dioxide, silicon oxynitride and the like. As shown, the passivation layers 103A, 103B exposes an appropriate portion of the contact areas 107D, 107T as is required for forming respective solder bumps in the device region 150D in a later manufacturing stage and for forming aluminum-based bond pads for wire bonding in the test region 150T. As previously explained, providing different contact regimes for connecting the device region 150D and the test region 150T to a respective carrier substrate may result in enhanced process efficiency with respect to obtaining test structures on the basis of the regions 150T.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following processes. Initially, the substrate 101 and any circuit elements contained therein may be manufactured on the basis of well-established process techniques, wherein, in sophisticated applications, circuit elements having critical dimensions on the order of magnitude of approximately 50 nm and less may be formed, followed by the fabrication of the one or more metallization layers 107 which may include copper-based metal lines and vias, wherein typically low-k dielectric materials are used for at least some of the dielectric material, such as the material 107A. Forming the metallization layer 107 may include the deposition of a cap layer 106, thereby confining any copper-based materials, such as the regions 107D, 107T. Next, the passivation layers 103A, 103B may be formed on the cap layer 106 on the basis of any appropriate deposition technique, such as plasma enhanced chemical vapor deposition (PECVD) and the like. Thereafter, a photolithography process is performed to provide a photoresist mask (not shown) having a shape and dimension that substantially determines the actual contact area for connecting to a bump structure in the device region 150D and to a wire bonding pad in the region 150T. Subsequently, the layer stack 103 may be opened on the basis of the previously defined resist mask, which may then be removed by well-established processes.
FIG. 1b schematically illustrates the conventional semiconductor device 100 in a further advanced manufacturing stage in which a barrier/adhesion layer 104 may be formed on the contact areas 107D, 107T, as well as on sidewall portions and a part of the horizontal portion of the passivation layers 103A, 103B. The barrier/adhesion layer 104 may, for instance, be comprised of tantalum, tantalum nitride, titanium, titanium nitride or other similar metals and compounds thereof as are typically used in combination with copper metallization systems in order to effectively reduce copper diffusion and enhance adhesion for an aluminum layer 105. Typically, the device 100 as shown in FIG. 1b may be formed by first depositing the barrier/adhesion layer 104, for instance, on the basis of sputter deposition techniques, followed by the deposition of the aluminum layer 105, for instance, on the basis of sputter deposition, chemical vapor deposition and the like. Next, a lithography process is performed, thereby forming a resist mask (not shown), which may be used as an etch mask during a reactive etch process, which may, for instance, be performed on the basis of complex chlorine-based etch chemistries to obtain the patterned aluminum layer 105 as shown in FIG. 1b. Furthermore, the respective etch process may also include a separate etch step for etching through the barrier/adhesion layer 104 followed by a wet chemical process for removing any corrosive etch residues generated during the complex aluminum etch step.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage in which a further passivation layer 103C is formed above the device 100, which may also be referred to as a final passivation layer, since the layer 103C may represent the last dielectric layer in and above which the bump structure is to be formed in the device region 150D. On the other hand, the passivation layer 103C which, in combination with the passivation layers 103A, 103B, may thus represent a final passivation layer stack 103, may be patterned so as to expose significant portions of the test region 150T, thereby providing a desired surface topography for enabling wire bonding of the respective aluminum layer 105 in a later stage. The passivation layer 103C may be provided in the form of a photosensitive polyimide material which may be patterned on the basis of photolithographical exposure and “development” to obtain the substantially exposed test region 150T and a respective opening for exposing at least a significant portion of the aluminum layer 105 in the device region 150D. After patterning the final passivation layer 103C, an appropriate resist mask (not shown) may be formed to define the lateral dimension of a solder bump in the device region 150D, while essentially covering the test region 150T so as to avoid deposition of solder material therein. It should be appreciated that the device region 150D may comprise a plurality of exposed aluminum-based metal regions in accordance with the device requirements, wherein substantially the entire surface area of the device region 150D may be available for providing respective solder bumps. On the other hand, the contact areas 107T in the test region 150T may be arranged with appropriate distances to allow for the required number of input/output terminals, while also respective pre-conditions are obtained for performing a wire bonding process in a later manufacturing stage during the assembly of a test structure on the basis of a test region 150T. Prior to forming the respective resist mask, an appropriate conductive liner system, which may also be referred to as underbump metallization layer system, may be formed which may comprise two or more separate layers with appropriate conductive materials, such as titanium, tungsten and the like, that are frequently used in view of diffusion blocking characteristics, adhesion and the like. Furthermore, one or more additional layers may be provided to act as an appropriate base layer for a subsequent electroplating process to fill in an appropriate solder material, such as tin and lead, or any other solder materials, such as lead-free compositions and the like, into openings defined in the resist mask.
FIG. 1d schematically illustrates the semiconductor device 100 after the above-described process sequence and after the removal of any resist material. Hence, the device 100 comprises a solder bump 109 formed on an underbump metallization layer 108, which may comprise two or more sub-layers 108A, 108B, depending on the process and device requirements. On the other hand, in the test region 150T, the aluminum layer 105 thus defines a bond pad that is configured for being wire bonded during the assembly of a respective test structure on the basis of the test region 150T, as previously explained.
Consequently, in the conventional approach described above, efficient wire bond techniques may be used for assembling the test region 150T while the solder bumps 109 may be provided in the device region 150D thereby, however, requiring a complex process sequence for depositing and patterning the barrier/adhesion layer 104 and the aluminum layer 105, while also resulting in significantly different passivation layer stacks in the device region 150D and the test region 150T. That is, due to the wire bonding process to be performed at a later stage, significant portions of the test region 150T may no longer include the final passivation layer 103C, which may reduce the authenticity of respective measurement results obtained on the basis of the test region 150T compared to the actual device regions 150D.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.